Most large-scale integrated circuits are presently packaged in plastic or ceramic packages with metal leads extended therefrom for soldering to a printed circuit board or for insertion into a socket. Typically, these IC packages are configured as dual-in-line or quad-in-line packages. In most instances only a single IC is contained within a package, although multiple chips are sometimes contained within a package. The circuit density resulting from this packaging technology is not very great, since the ceramic or plastic package consumes relatively large areas of the mounting surface, usually a printed circuit (PC) board, particularly if a socket is used.
A denser packaging technology is needed when mounting area or volume is limited or when speed considerations dictate that circuit elements be closely spaced. One such technology comprises the use of a ceramic substrate onto which ICs in an unpackaged form are directly attached to the ceramic mounting surface and are wire bonded to conductive areas on the mounting surface, or are inverted and connected directly to metallized areas on the ceramic mounting surface by, for example, a solder-pump technique. See, for examples, U.S. Pat. Nos. 3,927,815 to Mase, et al., 4,153,988 to Doo, 4,288,841 to Gogal and 4,549,200 to Ecker, et al. This technology, however, has several limitations. The ceramic material has a thermal coefficient of expansion different from that of the semiconductor material, and stresses on the mounting and bonding mechanisms occur. Also, interconnecting multiple ICs on a single ceramic mounting surface requires deposition of a metallic material in a pattern which desirably avoids cross-overs. Furthermore, the deposition of metallic conductors of extremely fine resolution is, on many surfaces, difficult. Additionally, if components, active or passive, are necessary to the circuit, discrete components must be used with their attendant problems of size and mounting mechanisms.
The thermal expansion coefficient mismatch between the integrated circuit chip and the mounting means or surface upon which IC chip is mounted has been addressed by others. For example, see C. N. Liu, et al. "Integrated Circuit Chip Package," IBM Technical Disclosure Bulletin, Vol. 17, No. 7, December 1974, p. 2018. In this package, the chips are not directly mounted onto the substrate, which has a different thermal expansion coefficient from the chips, but are supported above and cantilevered over the substrate by the means of rigid pedestals, which may undesirably consume excess vertical space.
Photocouplers provide additional examples of IC chips mounted on semiconductor substrates. For example, U.S. Pat. No. 4,122,479 to Sugawara, et al. discloses a gallium arsenide (GaAs) light emitting element mounted on a polysilicon light receiving element. While both structures are semiconductors, they are not necessarily thermally compatible. Indeed, the coefficient of thermal expansion for GaAs is over twice as much as that for silicon over normal operating temperatures including room temperature. The coefficient of thermal expansion can be expressed in one form as (.DELTA.L)/(L.DELTA.T) in units of K.sup.-1 where L is the length under consideration in any units, T is the temperature in degrees Kelvin (K). Throughout this discussion, the thermal expansion coefficients will have units of 10.sup.-6 K. According to the M. Neuberger, The Handbook of Electronic Materials, IFI/Plenum, 1971, Vol. 5, Group IV Semiconducting Materials, p. 37 and Vol. 2, Group III-V Semiconducting Materials, p. 45, silicon has a thermal expansion coefficient of 1.44 at 200 K. and 2.44 at 300K., whereas GaAs has a coefficient of 6.86 at 211-473K. 6.0 at 300K. Thus, GaAs expands twice the amount of silicon when heated over this range. While this difference may not have much of an effect over a single, point bond, it will place stresses on bonds on opposite edges of a VLSI chip mounted n inverted fashion which may wear out and break the bonds over many heating and cooling cycles. If the entire chip is mounted device-side-up on a substrate, severe stresses over the entire width of the chip could possibly crack the chip. Similar structures are seen in U.S. Pat. Nos. 4,092,614 to Sakuma, et al., 4,143,385 to Miyoshi, et al. and Japanese patent document No. 56-161681 to Fujitsu, et al. which disclose semiconductor chips mounted on semiconductor substrates, but do not specify the nature of the semiconductor materials in most instances and do not discuss the importance of choosing materials substantially similar to each other with respect to their thermal expansion properties.
U.S. Pat. No. 4,450,472 to Tuckerman, et al. teaches a semiconductor chip having improved heat dissipation capability by means of coolant chambers and microscopic channels which includes a cover that may be of the same semiconductor material as the chip. However, this structure is not otherwise similar to assemblies where IC chips having active devices therein are mounted on substrates also having active devices fabricated therein.
U.S. Pat. No. 3,698,082 to Hyltin, et al. describes a method for fabricating an integrated circuit array supporting substrate having coaxial transmission lines formed about a core in proper position for electrically connecting IC chips. The patent notes that the supporting substrate may be a strip transmission line comprised of a sheet of high resistivity silicon, intrinsic gallium arsenide or other material having a high resistivity or insulating properites. However, thermal expansion coefficient matching is not discussed and the substrate therein is not noted as bearing active devices.
D. J. Bodendorf, et al. in "Active Silicon Chip Carrier," IBM Technical Disclosure Bulletin, Vol. 15, No. 2, July 1972, p. 656 describe a silicon carrier substrate having silicon chips mounted thereon in "flip-chip" or inverted fashion. However, the chips are separated from the actual silicon substrate by interconnect and insulative layers. In addition, the silicon chips are described as mounted directly over the bipolar devices fabricated in the silicon carrier substrate risking possible damage to the underlying bipolar devices during the bonding of the silicon chips.
It is an object of the instant invention to provide an improved mounting surface for semiconductor devices.
It is a further object of the invention to overcome the thermal expansion problems of ceramic mounting materials of different composition for the integrated circuit.
It is another object of the invention to provide a mechanism for incorporating off-chip elements, active or passive, in a layout-efficient manner.
It is an additional object of the invention to provide a layout-efficient mechanism for interconnecting multiple ICs on a single mounting substrate.
It is another object of the invention to provide an IC mounting surface which may be used to fabricate semiconductor components which may be interconnected or connected to the integrated circuits mounted thereon.
Another object of the invention is to provide a means for increasing the density of integrated devices without placing chips on tops of devices formed in the substrate.